Sparse matrix dense vector multliplication circuitry

A circuit arrangement for multiplying a sparse matrix by a dense vector, comprising:

• a first switching circuit (302) having N input ports and N output ports and configured to route input triplets from the N input ports to the N output ports based on column indices of the triplets, wherein N≥2, and each triplet includes a non-zero value, a row index, and a column index;
• N first memory banks (303) coupled to the output ports of the first switching circuit respectively, wherein each first memory bank is configured to store a subset of a plurality of vector elements and has a read-address port coupled to input the column index of the triplet from the respective output port of the first switching circuit;
• N multipliers (305) coupled to read-data ports of the N first memory banks, respectively, and to the N output ports of the first switching circuit, respectively, wherein each multiplier is configured to multiply the non-zero value of the triplet from the respective output port of the first switching circuit by the vector element from the read-data port of the respective first memory bank;
• a second switching circuit (304) having N input ports coupled to the N output ports of the first switching circuit and to the N multipliers and configured to route tuples from the N input ports to N output ports based on row indices of the tuples, wherein each tuple includes a product output by the one of the N multipliers and a row index output by one of the N output ports of the first switching circuit;
• and
• N accumulator circuits (307) coupled to the N output ports of the second switching circuit, respectively, wherein each accumulator circuit is configured to sum products of tuples having equal row indices.