Multi-Instruction Engine-Based Instruction Processing Method and Processor

Abstract

A processor includes a program block dispatcher, an instruction cache group, and an instruction engine group. A plurality of instruction caches in the instruction cache group are in a one-to-one correspondence with a plurality of instruction engines in the instruction engine group. In a method, the program block dispatcher determines, based on an instruction processing request for processing a first instruction set, a first instruction engine for processing the first instruction set; and determines, based on the one-to-one correspondence between the instruction engines and the instruction caches, a first instruction cache configured to cache the first instruction set. The program block dispatcher sends a program counter in the instruction processing request to the first instruction cache. The first instruction engine obtains the first instruction set from the first instruction cache, to execute an instruction in the first instruction set.

Dependencies are inferred from the claim text.