US 2023/0266992 A1 · PROCESSOR FOR MANAGING RESOURCES USING DUAL QUEUES, AND OPERATING METHOD THEREOF

Abstract

A method for managing resources by using a processor that includes a first queue and a second queue includes receiving, by the processor, input/output commands from a virtual device, generating, by the processor, interrupts that each includes a process address space identifier (PASID) that corresponds to each of the input/output commands, storing, by the processor, the interrupts in the first queue, storing, by the processor, in a memory device, data that respectively corresponds to each of the interrupts, and storing, by the processor, in the second queue, location information indicating a storage location of the data stored in the memory device and size information indicating a size of the data.

Claims20

Dependent claims

A method for managing resources by using a processor that includes a first queue and a second queue, the method comprising:

receiving, by the processor, input/output commands from a virtual device;
generating, by the processor, interrupts that each includes a process address space identifier (PASID) that corresponds to one of the input/output commands;
storing, by the processor, the interrupts in the first queue;
storing, by the processor, in a memory device, data that respectively corresponds to each of the interrupts;
and
storing, by the processor, in the second queue, location information that indicates a storage location of the respective data stored in the memory device and size information that indicates a size of the respective data.

3 more elements

A processor, comprising:

a first queue and a second queue,
wherein the processor executes a process address space identifier (PASID) allocation computer program, a first queue management computer program, and a second queue management computer program.
wherein the PASID allocation computer program receives input/output commands from virtual devices and generates interrupts that each include a PASID that corresponds to one of the input/output commands,
wherein the first queue management computer program receives the interrupts generated by the PASID allocation computer program and stores the interrupts in the first queue, and wherein the second queue management computer program stores, in a memory device, data that respectively corresponds to each of the interrupts in response to each of the interrupts received from the PASID allocation computer program or the first queue management computer program, and stores in the second queue location information that indicates a storage location of the data that is stored in the memory device, and size information that indicates a size of the data.

1 more element

A processor, comprising:

a process address space identifier (PASID) management computer program, a second queue management computer program, a first hardware queue, and a second hardware queue,
wherein the PASID management computer program receives input/output commands from virtual devices, generates interrupts that each include a PASID that corresponds to each of the input/output commands, and stores the interrupts in the first hardware queue, and
wherein the second queue management computer program stores data that respectively corresponds to each of the interrupts in a memory device in response to each of the interrupts received from the PASID management computer program, and stores, in the second hardware queue, location information that indicates a storage location of the data that is stored in the memory device, and size information that indicates a size of the respective data.

Dependencies are inferred from the claim text.

Processor for managing resources using dual queues, and operating method thereof

Life of this patent

Processor for managing resources using dual queues, and operating method thereof

Life of this patent

Abstract

Claims20