Transistor with interdigit electrodes, comprising a gate terminal connected by a plurality of vertical vias to the gate electrodes

A device, comprising:

• a substrate having a first surface, the first surface including an active region of a transistor;
• a first transistor cell and a second transistor cell adjacent to each other on the substrate, each one of the first and second transistor cells having a source electrode, drain electrode, and gate electrode;
• a source terminal at a first end of the active region, the source terminal being coupled to the source electrodes;
• a drain terminal opposite the source terminal, the drain terminal being coupled to the drain electrodes;
• a first dielectric layer on the source terminal, on the drain terminal, and on the gate electrodes;
• a gate terminal being spaced from the gate electrodes by the first dielectric layer;
• and
• a plurality of conductive vias through the first dielectric layer extending toward the first surface and coupled between the gate electrodes and the gate terminal.

A transistor comprising:

• a substrate;
• a gate terminal on a first surface of the substrate;
• a source terminal on a second surface of the substrate;
• a drain terminal opposite the source terminal on the second surface of the substrate;
• a plurality of source electrodes extending from the source terminal toward the drain terminal;
• a plurality of drain electrodes extending from the drain terminal toward the source terminal;
• and
• a plurality of gate electrodes between adjacent ones of the plurality of drain electrodes and the plurality of source electrodes, the plurality of gate electrodes being spaced from the gate terminal by the substrate, each gate electrode including:
• a plurality of conductive vias that extend through the substrate to the gate terminal.