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US 2023/0157035 A1Published application
Multi-layer interconnect
AssigneeIntel Corporation
InventorsShafaat Ahmed, Viswas Reddy Pola, Gregory C. Herdt
Life of this patent
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Abstract
An apparatus comprising a substrate; and an interconnect comprising a first metal layer between and in contact with a second metal layer and a third metal layer, wherein the first metal layer has a resistivity that is lower than a resistivity of the second metal layer and a resistivity of the third metal layer.
Claims21
A memory device including:
- a three dimensional crosspoint memory array comprising a plurality of memory cells and a plurality of access lines coupled to the plurality of memory cells, wherein an access line of the plurality of access lines comprises a first metal layer between and in contact with a second metal layer and a third metal layer, wherein the first metal layer has a resistivity that is lower than a resistivity of the second metal layer and a resistivity of the third metal layer.
A method comprising:
- depositing, on a substrate, a metal stack comprising a first metal layer between and in contact with a second metal layer and a third metal layer, wherein the first metal layer has a resistivity that is lower than a resistivity of the second metal layer and a resistivity of the third metal layer;
- and
- etching the metal stack to form an interconnect.
An apparatus comprising:
- a substrate;
- and
- an interconnect comprising a first metal layer between and in contact with a second metal layer and a third metal layer, wherein the first metal layer has a resistivity that is lower than a resistivity of the second metal layer and a resistivity of the third metal layer.
Dependencies are inferred from the claim text.