Three-dimensional memory device and method for forming the same

A system, comprising:

• a three-dimensional (3D) memory device configured to store data, the 3D memory device comprising:
• a plurality of memory stacks comprising a first memory stack and a second memory stack arranged along a first direction, each memory stack comprising:
• a plurality of first conductive layers and a plurality of first dielectric layers alternately stacked along a second direction perpendicular to the first direction;
• and
• a channel structure extending through the plurality of first conductive layers and the plurality of first dielectric layers along the second direction;
• a dummy structure disposed between the first memory stack and the second memory stack, the dummy structure extending along a second direction perpendicular to the first direction and a third direction perpendicular to the first direction and the second direction;
• a first isolation structure disposed between the dummy structure and the first memory stack, the first isolation structure extending along the second direction and the third direction;
• a second isolation structure disposed between the dummy structure and the second memory stack, the second isolation structure extending along the second direction and the third direction;
• a semiconductor layer disposed under the plurality of memory stacks, the dummy structure, the first isolation structure, and the second isolation structure;
• and
• a trench isolation structure disposed in the semiconductor layer extending along the second direction and the third direction;
• and
• a memory controller coupled to the 3D memory device and configured to control operations of the 3D memory device.

A method for forming a three-dimensional (3D) memory device, comprising:

• forming a stack structure comprising a plurality of first dielectric layers and a plurality of sacrificial layers alternatingly arranged on a semiconductor layer, wherein the stack structure comprises a plurality of dielectric stacks arranged along a first direction;
• forming a plurality of channel structures in the stack structure along a second direction perpendicular to the first direction;
• forming a first opening and a second opening in the stack structure from an upper side of the stack structure along the second direction and a third direction perpendicular to the first direction and the second direction, wherein the plurality of dielectric stacks are zoned into a first memory region, a second memory region, and a dummy region by the first opening and the second opening, the dummy region is disposed between the first memory region and the second memory region, the first opening is disposed between the first memory region and the dummy region, and the second opening is disposed between the second memory region and the dummy region;
• replacing the plurality of sacrificial layers with a plurality of conductive layers;
• forming a first isolation structure in the first opening and a second isolation structure in the second opening;
• and
• forming a third isolation structure in the semiconductor layer under the first isolation structure and forming a fourth isolation structure in the semiconductor layer under the second isolation structure.