Semiconductor device including data storage pattern

A semiconductor device comprising:

• a semiconductor substrate;
• a peripheral circuit region on the semiconductor substrate;
• a conductive layer on the peripheral circuit region;
• a first polysilicon layer on the conductive layer;
• a stack structure on the first polysilicon layer;
• and
• a vertical structure penetrating through the stack structure and contacting at least one of the first polysilicon layer and the conductive layer,
• wherein the stack structure includes a plurality of gate layers and a plurality of interlayer insulating layers alternately stacked on the first polysilicon layer,
• wherein the vertical structure includes an insulating core region, a channel layer, and a plurality of data storage patterns,
• wherein the insulating core region extends in a vertical direction, the vertical direction being perpendicular to an upper surface of the semiconductor substrate,
• wherein the channel layer includes a first portion between the stack structure and the insulating core region and a second portion contacting the first polysilicon layer,
• wherein the plurality of data storage patterns are between the channel layer and the plurality of gate layers in a horizontal direction parallel to the upper surface of the semiconductor substrate, and are spaced apart from each other in the vertical direction, and
• wherein a lowermost data storage pattern among the plurality of data storage patterns is at a higher level than the first polysilicon layer.

A semiconductor device comprising:

• a first structure including a first substrate, a second substrate, and a peripheral circuit region between the first substrate and the second substrate;
• a second structure including a plurality of gate layers and a plurality of interlayer insulating layers alternately stacked, and overlapping the first structure in a vertical direction perpendicular to an upper surface of the first substrate;
• and
• a vertical structure penetrating through the stack structure in the vertical direction and contacting the second substrate of the first structure,
• wherein the vertical structure includes:
• an insulating core region extending in the vertical direction;
• a channel layer on a side surface of the insulating core region;
• a first dielectric layer between the stack structure and the channel layer;
• a second dielectric layer between the stack structure and the first dielectric layer;
• and
• a plurality of data storage patterns between first dielectric layer and the second dielectric layer, and spaced apart from each other in the vertical direction,
• wherein the plurality of data storage patterns are adjacent to the plurality of gate layers in a horizontal direction parallel to the upper surface of the first substrate,
• wherein the plurality of data storage patterns include a first data storage pattern adjacent to a first gate layer of the plurality of gate layers in the horizontal direction,
• wherein the first data storage pattern has a first side surface facing the first gate layer and a second side surface facing the channel layer,
• wherein the second side surface of the first data storage pattern has a concave portion, and
• wherein the second dielectric layer contacts the second side surface of the first data storage pattern and a portion of the first dielectric layer.

A semiconductor device comprising:

• a first structure including a first substrate, a second substrate, and a peripheral circuit region between the first substrate and the second substrate;
• a second structure including a plurality of gate layers and a plurality of interlayer insulating layers alternately stacked, and overlapping the first structure in a vertical direction perpendicular to an upper surface of the first substrate;
• and
• a vertical structure penetrating through the stack structure in the vertical direction and contacting the second substrate of the first structure,
• wherein the vertical structure includes:
• an insulating core region extending in the vertical direction;
• a channel layer on a side surface of the insulating core region;
• a first dielectric layer between the stack structure and the channel layer;
• a second dielectric layer between the stack structure and the first dielectric layer;
• and
• a plurality of data storage patterns between first dielectric layer and the second dielectric layer, and spaced apart from each other in the vertical direction,
• wherein the plurality of data storage patterns are adjacent to the plurality of gate layers in a horizontal direction parallel to the upper surface of the first substrate,
• wherein the plurality of data storage patterns include a first data storage pattern adjacent to a first gate layer of the plurality of gate layers in the horizontal direction, and
• wherein at least one of an upper surface and a lower surface in each of the first data storage pattern.