Semiconductor memory device and method of fabricating the same

A semiconductor memory device, comprising:

• a stack including layer groups vertically stacked on a substrate, each of the layer groups including a word line, a lower channel layer, an upper channel layer, and a data storing element electrically connected to the lower channel layer and the upper channel layer;
• and
• a bit line at a side of the stack, the bit line extending vertically,
• wherein:
• in each of the layer groups, the upper channel layer and the lower channel layer are vertically separated from each other,
• the word line of each of the layer groups extends horizontally between the lower channel layer and the upper channel layer,
• the lower channel layer and the upper channel layer of each of the layer groups are electrically connected to the bit line,
• the layer groups include a first layer group and a second layer group, which are sequentially stacked, and
• a first vertical distance between the lower channel layer of the first layer group and the upper channel layer of the first layer group is different from a second vertical distance between the upper channel layer of the first layer group and the lower channel layer of the second layer group.

A semiconductor memory device, comprising:

• a stack including layer groups vertically stacked on a substrate, each of the layer groups including a memory cell transistor and a data storing element electrically connected to the memory cell transistor;
• and
• a bit line at a side of the stack, the bit line extending vertically,
• wherein:
• the bit line electrically connects the stacked memory cell transistors of the layer groups to each other,
• the memory cell transistor of each of the layer groups includes:
• a lower channel layer between the bit line and the data storing element;
• an upper channel layer between the bit line and the data storing element, the upper channel layer being vertically separated from the lower channel layer;
• and
• a word line between the lower channel layer and the upper channel layer,
• the word line of each of the layer groups includes:
• a gate portion sandwiched between and overlapped with the lower channel layer and the upper channel layer;
• and
• a connecting portion connecting the gate portions that are adjacent to each other, and
• a width of the gate portion is larger than a width of the connecting portion, as measured in a same direction.