US 2023/0156995 A1Published application

Four cpp wide memory cell with buried power grid, and method of fabricating same

AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.

InventorsHidehiro FUJIWARA, Chih-Yu LIN, Yen-Huei CHEN, Wei-Chang ZHAO, Yi-Hsin NIEN

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Abstract

A memory device includes active regions and gate structures, each of the gate structures is electrically coupled to a first portion of a corresponding active region of the active regions. The memory device includes contact-to-transistor-component structures (MD structures), each of the MD structures is over a second portion of a corresponding active region, and a first MD structure is between adjacent gate structures. The memory device includes via-to-gate/MD (VGD) structures, each of the VGD structures is over to a corresponding gate electrode and MD structure. The memory device includes conductive segments, each of the conductive segments is over and electrically coupled to a corresponding VGD structure. The memory device includes buried contact-to-transistor-component structures (BVD) structures, each of the BVD structures is under a third portion of a corresponding active region. The memory device includes buried conductive segments, each of the buried conductive segments is under a corresponding BVD structure.

Claims20

Dependent claims

A semiconductor device comprising:

first and second write-word lines;
and
first and second memory cells, each of which includes:
a latch;
a first pass gate coupled between an input node of the latch and a bit line;
a second pass gate coupled between an output node of the latch and a bit_bar line;
the latch and the first and second pass gates being in a transistor layer;
and
gate electrodes of the first and second pass gates being coupled to a corresponding one of the first or second write-word lines;
gate lines which are correspondingly over the active regions transistor layer and which have corresponding long axes extending in a first direction;
for each latch, gate electrodes of transistors included therein being coupled correspondingly to the gate lines;
and
the gate lines being organized into first, second, third and fourth sets which are non-overlapping relative to a second direction substantially perpendicular to the first direction, each set including two or more of the gate lines which have substantially collinear long axes;
and
each of the first and second memory cells being coupled to a corresponding one of the gate lines in each of the first, second, third and fourth sets such that each of the first and second memory cells is a four contacted poly pitch memory cell;
and
power grid lines for the transistors and the pass gates being underneath the transistor layer.

14 more elements

A method of forming a memory device, the method comprising:

forming active regions in a substrate;
forming gate electrodes over and electrically coupled to corresponding first portions of corresponding ones of the active regions the gate electrodes being substantially aligned relative to four corresponding track lines such that the memory device has a width of four contacted poly pitch (4 CPP) relative to a direction perpendicular to long axes of the gate electrodes;
forming contact-to-transistor-component structures (MD structures) over and electrically coupled to corresponding second portions of corresponding ones of the active regions, the MD structures being interspersed among corresponding ones of the gate electrodes;
forming via-to-gate/MD (VGD) structures over and electrically coupled to corresponding ones of the gate electrodes and the MD structures;
forming unburied conductive segments over and electrically coupled to corresponding ones of the VGD structures, the unburied conductive segments being in a first unburied layer of metallization;
forming buried contact-to-transistor-component structures (BVD structures) under and electrically coupled to corresponding third portions of corresponding ones of the active regions;
and
forming buried conductive segments under and electrically coupled to corresponding ones of the BVD structures, the buried conductive segments being in a first buried layer of metallization, and correspondingly providing a first reference voltage or a second reference voltage.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/155,932Filed 18 Jan 2023
Priority: 29 Jun 2020
Published: 18 May 2023
Term ends: Not estimatedThe source records don’t support an estimate.

Classification12 codes

H10B 10/12
Static random access memory [SRAM] devices: comprising a MOSFET load element
H10D 89/10
Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00: integrated device layouts
G06F 30/392
Circuit design at the physical level: floor-planning or layout, e.g. partitioning or placement
H10W 20/20
Interconnections in chips, wafers or substrates: interconnections within wafers or substrates, e.g. through-silicon vias [TSV]

Family

Application63/045,483Us provisional application · filed 29 Jun 2020
Application17/225,627Continuation · filed 8 Apr 2021
Application18/155,932Continuation
US 11,569,246 B2Related patent
US 12,137,548 B2Related patent
US 2021/0408011 A1Published application
US 2023/0156995 A1This patent

From the US filing history. Foreign family members aren’t listed.

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