Analog-to-digital converting circuit using output voltage clipping and operation method thereof

A circuit, comprising:

• a first amplifier configured to operate based on a first power supply voltage and to generate a first output signal by equalizing voltage levels of input nodes and output nodes in response to a first auto-zero signal in a first auto-zero period, comparing a ramp signal and a reset signal of a pixel signal output from a pixel array in a first operation period, and comparing the ramp signal and an image signal of the pixel signal output from the pixel array in a second operation period;
• a second amplifier configured to operate based on the first power supply voltage, to charge a capacitor in response to a second auto-zero signal in a second auto-zero period, and to generate a second output signal based on the first output signal;
• and
• a counter configured to operate based on a second power supply voltage, to count pulses of the second output signal, and to output a counting result as a digital signal,
• wherein a first level of the first power supply voltage is greater than a second level of the second power supply voltage,
• wherein the second amplifier is further configured to adjust a voltage level of the second output signal from a low level to a third level, wherein the third level is less than or equal to the second level of the second power supply voltage,
• wherein, during at least one of the first operation period and the second operation period, the second output signal controls a power current of the second amplifier, and
• wherein an operation of the second amplifier is stopped from a first time at which the second auto-zero period ends to a second time at which the first operation period starts.

A circuit which operates a first power supply voltage and generates an output signal in an operation period, comprising:

• a first transistor configured to provide a power supply voltage to a first output node from which the output signal is output;
• a clipping circuit coupled between a power supply voltage terminal and the first transistor, and configured to adjust a voltage level of the output signal to be lower than a level of the first power supply voltage, by making a voltage drop between the power supply voltage terminal and the first transistor;
• and
• a current source coupled with the first transistor through the first output node, and configured to generate a power current.