3d semiconductor device and structure with memory

A semiconductor device, the device comprising:

• a first level comprising a plurality of transistors,
• wherein said plurality of transistors comprise first single crystal silicon;
• a first metal layer disposed over said first level;
• a second metal layer disposed over said first metal layer;
• an isolation layer disposed over said second metal layer;
• a first silicon layer comprising second single crystal silicon,
• wherein said first silicon layer is disposed over said isolation layer, and
• wherein said isolation layer comprises an oxide to oxide bonding surface;
• and
• a plurality of capacitors,
• wherein said plurality of capacitors comprise functioning as a decoupling capacitor to mitigate power supply noise.

A semiconductor device, the device comprising:

• a first level comprising a plurality of transistors,
• wherein said plurality of transistors comprise first single crystal silicon;
• a first metal layer disposed over said first level;
• a second metal layer disposed over said first metal layer;
• an isolation layer disposed over said second metal layer;
• a first silicon layer comprising second single crystal silicon disposed over said isolation layer,
• wherein said isolation layer comprises an oxide to oxide bonding surface;
• and
• a plurality of vias disposed through said first level,
• wherein at least one of said vias comprise contact to at least one of said transistor.