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US 2023/0154979 A1Published application
Method of manufacturing semiconductor devices and semiconductor devices
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsShahaji B. MORE, chandrashekhar Prakash SAVANT
Life of this patent
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Abstract
A gate structure of a field effect transistor includes a first gate dielectric layer, a second gate dielectric layer, and one or more conductive layers disposed over the first gate dielectric layer and the second gate dielectric layer. The first gate dielectric layer is separated from the second gate dielectric layer by a gap filled with a diffusion blocking layer.
Claims20
A method of manufacturing a semiconductor device, comprising:
- forming a first gate dielectric layer in a gate space, the gate space being laterally surrounded by one or more insulating layers;
- forming a second gate dielectric layer over the first gate dielectric layer;
- separating the first and second gate dielectric layers into a first stacked gate dielectric layer and a second stacked gate dielectric layer by forming a trench;
- forming one or more work function adjustment material (WFM) layers over the first stacked gate dielectric layer and the second stacked gate dielectric layer;
- and
- forming a body gate electrode layer over the one or more WFM layers.
3 more elements
A method of manufacturing a semiconductor device, comprising:
- forming a first gate dielectric layer over a first channel region made of a first semiconductor material and over an isolation insulating layer;
- forming a second gate dielectric layer over a second channel region made of a second semiconductor material and over the isolation insulating layer, the first gate dielectric layer being laterally in contact with the second gate dielectric layer at a boundary located over the isolation insulating layer;
- forming a third gate dielectric layer over the first and second gate dielectric layers;
- separating, by using a patterning operation, the third gate dielectric layer, the first gate dielectric layer and the second gate dielectric layer by a trench;
- and
- forming a diffusion barrier by filling the trench with a dielectric material or a conductive material, wherein:
- at least one of the first gate dielectric layer or the second gate dielectric layer includes a dopant, and
- a dopant concentration is different between the first gate dielectric layer and the second gate dielectric layer.
5 more elements
A method of manufacturing a semiconductor device, comprising:
- forming a pair of first gate spaces and a pair of second gate spaces;
- forming a first gate dielectric layer in the pair of first gate spaces and a second gate dielectric layer in the pair of second gate spaces;
- forming a third gate dielectric layer over the first and second gate dielectric layers;
- separating, by using a patterning operation, the third gate dielectric layer the first gate dielectric layer and the second gate dielectric layer by a trench that connects the pair of first gate spaces and the pair of second gate spaces;
- and
- forming one or more work function adjustment material (WFM) layers over the third gate dielectric layer in the pair of first gate spaces and over the third gate dielectric layer in the pair of second gate spaces;
- and
- forming a body gate electrode layer over the one or more WFM layers,
- wherein a part of the one or more WFM layers fills the trench.
6 more elements
Dependencies are inferred from the claim text.