Device with alternate complementary channels and fabrication method thereof

A method comprising:

• forming a layer stack on a substrate, the layer stack comprising an n-type field effect transistor (NFET) channel layer, a p-type field effect transistor (PFET) channel layer, and a sacrificial layer between the NFET channel layer and the PFET channel layer;
• performing a first selective etching process to opposite first sidewalls of the layer stack, wherein the first selective etching process etches the NFET channel layer at a faster etch rate than etching the PFET channel layer;
• after performing the first selective etching process, forming p-type epitaxial structures on the first sidewalls of the layer stack;
• performing a second selective etching process to opposite second sidewalls of the layer stack, wherein the second selective etching process etches the PFET channel layer at a faster etch rate than etching the NFET channel layer;
• after performing the second selective etching process, forming n-type epitaxial structures on the second sidewalls of the layer stack;
• and
• replacing the sacrificial layer with a gate structure.

A device comprising:

• a gate structure over a substrate;
• n-type source/drain features and p-type source/drain features disposed around the gate structure, wherein from a top view, the gate structure has a quadrilateral profile, the n-type source/drain features are respectively at opposite first and second sides of the quadrilateral profile of the gate structure, and the p-type source/drain features are respectively at opposite third and fourth sides of the quadrilateral profile of the gate structure;
• an NFET channel extending within the gate structure and connecting the n-type source/drain features;
• and
• a PFET channel extending within the gate structure and connecting the p-type source/drain features, the NFET channel and the PFET channel being vertically spaced apart by the gate structure from a cross-sectional view.