Semiconductor package

A semiconductor package, comprising:

• a lower redistribution substrate that includes a dielectric layer and a wiring pattern in the dielectric layer, the wiring pattern including:
• a line part that extends horizontally, and
• a via part connected to the line part, a width of the via part being less than a width of the line part;
• a passivation layer on a top surface of the lower redistribution substrate;
• a conductive pillar that penetrates the passivation layer, the conductive pillar being connected to the via part;
• a connection terminal on a top surface of the conductive pillar;
• a semiconductor chip on the connection terminal;
• a molding layer covering the semiconductor chip and filling a space between the passivation layer and the semiconductor chip on the passivation layer;
• an upper redistribution layer on the molding layer;
• and
• a conductive via that is spaced apart from the semiconductor chip and penetrates the molding layer, the conductive via connecting the lower redistribution substrate and the upper redistribution layer,
• wherein the molding layer covers a portion of a lateral surface of the conductive pillar.

A semiconductor package, comprising:

• a redistribution substrate that includes a dielectric layer and a wiring pattern in the dielectric layer;
• a first passivation layer on a bottom surface of the redistribution substrate;
• a conductive pillar that penetrates the first passivation layer, the conductive pillar being connected to the wiring pattern;
• a first connection terminal on a bottom surface of the conductive pillar;
• a second passivation layer on a top surface of the redistribution substrate;
• a conductive support pattern that penetrates the second passivation layer, the conductive support pattern being connected to the wiring pattern;
• a second connection terminal on the conductive support pattern;
• a semiconductor chip on the second connection terminal;
• and
• a molding layer covering the second connection terminal and the semiconductor chip on the second passivation layer,
• wherein the conductive support pattern extends on a top surface of the second passivation layer, and
• wherein the first passivation layer contacts a portion of a lateral surface of the conductive pillar and exposes another portion of the lateral surface of the conductive pillar.