US 2023/0148253 A1 · FLEXIBLE AND LOW POWER CACHE MEMORY ARCHITECTURE

Abstract

A low power caching architecture is disclosed. The architecture includes multiple data memory regions, each including a cache memory. The data memory regions are coupled to a peripheral device. A host processor is operable to control power to each of the plurality of data memory regions. The host processor is operable to power on any of data memory regions and power down any unused data memory regions of the data memory regions. A cache control logic is operable to receive a data request from the host processor. The cache control logic requests the data from the peripheral. The host processor powers on at least one of the data memory regions, and stores the requested data in the cache memory of the powered on data memory region.

Claims20

Dependent claims

A system on chip comprising:

a peripheral interface coupled to a peripheral device storing data;
a plurality of data memory regions, each including a cache memory, the data memory regions coupled to the peripheral device;
a host processor operable to control power to each of the plurality of data memory regions, wherein the host processor is operable to power on any of the plurality of data memory regions and power down any unused data memory regions of the plurality of data memory regions;
and
a cache control logic operable to receive a data request from the host processor, the cache control logic requesting the data from the peripheral device, and wherein the host processor powers on at least one of the plurality of data memory regions, and stores the requested data in the cache memory of the at least one of the data memory regions.

2 more elements

Dependencies are inferred from the claim text.

Flexible and low power cache memory architecture

Life of this patent

Flexible and low power cache memory architecture

Life of this patent

Abstract

Claims20