Planar transistor device comprising at least one layer of a two-dimensional (2d) material

A planar transistor device comprising a gate having a gate length that extends in a gate length direction and a gate width that extends in a gate width direction, the transistor comprising:

• a gate structure positioned above a semiconductor substrate, the semiconductor substrate comprising a substantially planar upper surface;
• a channel region;
• a source region;
• a drain region;
• and
• at least one layer of a two-dimensional (2D) material that is positioned in at least one of the source region, the drain region or the channel region, wherein the at least one layer of 2D material has a substantially planar upper surface, a substantially planar bottom surface and a substantially uniform vertical thickness across an entire length of the at least one layer of 2D material in the gate length direction and across an entire width of the at least one layer of 2D material in the gate width direction, wherein the substantially planar upper surface and the substantially planar bottom surface of the at least one layer of 2D material are positioned approximately parallel to a substantially planar surface of the semiconductor substrate;
• wherein the at least one layer of 2D material extends across an entirety of the source region, an entirety of the channel region and an entirety of the drain region,
• wherein the at least one layer of 2D material comprises a plurality of layers of 2D material positioned in a vertically stacked arrangement, and
• wherein the device further comprises a first conductive source/drain contact structure that is conductively coupled to an uppermost layer of the plurality of layers of 2D material in the source region and a second conductive source/drain contact structure that is conductively coupled to an uppermost layer of the plurality of layers of 2D material in the drain region.

A planar transistor device comprising a gate having a gate length that extends in a gate length direction and a gate width that extends in a gate width direction, the transistor comprising:

• a gate structure positioned above a semiconductor substrate, the semiconductor substrate comprising a substantially planar upper surface, the gate structure comprising an upper surface;
• a channel region;
• a source region;
• a drain region;
• a plurality of layers of two-dimensional (2D) material that is positioned across an entirety of the source region and across an entirety of the drain region, wherein the channel region is substantially free of the plurality of layers of 2D material, wherein each of the plurality of layers of 2D material has a substantially planar upper surface, a substantially planar bottom surface and a substantially uniform vertical thickness across an entire length of the plurality of layers of 2D material in the gate length direction and across an entire width of the plurality of layers of 2D material in the gate width direction, wherein the substantially planar upper surface and the substantially planar bottom surface of each of the plurality of layers of 2D material are positioned approximately parallel to the substantially planar upper surface of the semiconductor substrate, wherein an uppermost layer of the plurality of layers of 2D material in the source region and an uppermost layer of the plurality of layers of 2D material in the drain region have an upper surface that is positioned at a level that is above a level of the upper surface of the gate structure;
• and
• a sidewall spacer positioned adjacent the gate structure between the plurality of layers of 2D material in the source region and the plurality of layers of 2D material in the drain region.