Asynchronous Reset Physically Unclonable Function Circuit

Abstract

A NCL circuit is disclosed with a combinational logic circuit between DI register banks, an input register bank having at least a first input register positioned upstream of an output register bank having at least a first output register. A completion logic circuit that sends a handshaking signal to the upstream input registers indicating that all the downstream circuits are ready for any one of two wavefronts, meaningful data wavefront and a NULL wavefront from the combination logic circuit. The NCL circuit may further have one or more observation points on outrail groups of the input registers, observing propagation of startup values to the combination logic circuit. The NCL circuit may also have one or more multiplexers allowing for selection of a primary input or the feedback signal, to control the start up values to the combinational logic circuit will powering on.

Dependencies are inferred from the claim text.