Securely exposing an accelerator to privileged system components
AssigneeIntel Corporation
InventorsJOSHUA FENDER, UTKARSH Y. KAKAIYA, MOHAN NAIR, BRAIN MORRIS, PRATIK MAROLIA
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AssigneeIntel Corporation
InventorsJOSHUA FENDER, UTKARSH Y. KAKAIYA, MOHAN NAIR, BRAIN MORRIS, PRATIK MAROLIA
Estimating the term…
Various embodiments are generally directed to securing systems that include hardware accelerators, such as FPGA-based accelerators, and privileged system components. Some embodiments may provide a security broker. In various embodiments, the security broker may provide interfaces between the hardware accelerator and the privileged component. Some embodiments may receive an instruction from the hardware accelerator targeting the privileged component, and validate the instruction based on a configuration. In some embodiments, upon determining the instruction is not validated, the instruction is restricted from further processing.
1-20. (canceled)
An apparatus, comprising:
At least one non-transitory computer-readable medium, comprising instructions that when executed by a security broker coupled to a hardware accelerator and a privileged component, cause the security broker to:
A system, comprising:
A system, comprising:
Dependencies are inferred from the claim text.