Process Loading Remediation

A method, comprising:

• forming first and second arrays of structures on a semiconductor substrate;
• blocking the second array of structures with a first mask while exposing the first array;
• applying a first treatment to the first array of structures;
• blocking the first array of structures with a second mask while exposing the second array of structures;
• and
• applying a second treatment to the second array of structures, wherein the second treatment is different from the first treatment.

A structure, comprising:

• a substrate;
• a first array of polysilicon structures on the substrate, the first array being associated with logic devices and having a first pitch;
• first spacers of a first width formed on sidewalls of polysilicon structures in the first array;
• a second array of polysilicon structures on the substrate, the second array being associated with analog devices and having a second pitch;
• and
• second spacers of a second width formed on sidewalls of polysilicon structures in the second array.