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US 2023/0145317 A1Published application
Metal layers for increasing polarization of ferroelectric memory device
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYen-Chieh Huang, Hai-Ching Chen, Chung-Te Lin
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Abstract
Various embodiments of the present disclosure are directed towards an integrated chip including a semiconductor layer overlying a substrate. A ferroelectric layer overlies the substrate. A pair of source/drain structures are disposed on the semiconductor layer. A lower metal layer is disposed along a lower surface of the ferroelectric layer. An upper metal layer is disposed along an upper surface of the ferroelectric layer.
Claims20
An integrated chip, comprising:
- a semiconductor layer overlying a substrate;
- a ferroelectric layer overlying the substrate;
- a pair of source/drain structures disposed on the semiconductor layer;
- a lower metal layer disposed along a lower surface of the ferroelectric layer;
- and
- an upper metal layer disposed along an upper surface of the ferroelectric layer.
3 more elements
An integrated chip, comprising:
- a ferroelectric layer over a substrate, wherein the ferroelectric layer has a first side opposite a second side;
- a semiconductor layer disposed on the first side of the ferroelectric layer;
- a source/drain structure disposed on the semiconductor layer;
- a lower metal layer disposed between the first side of the ferroelectric layer and the semiconductor layer;
- and
- an upper metal layer disposed on the second side of the ferroelectric layer, wherein a thickness of the upper metal layer is greater than a thickness of the ferroelectric layer.
3 more elements
A method for forming an integrated chip, the method comprising:
- depositing a lower metal layer over a substrate;
- depositing a ferroelectric layer on the lower metal layer;
- depositing an upper metal layer on the ferroelectric layer;
- depositing a semiconductor layer on the upper metal layer;
- forming a pair of source/drain structures on the semiconductor layer;
- and
- wherein a coefficient of thermal expansion (CTE) of the ferroelectric layer is greater than a CTE of the upper metal layer and a CTE of the lower metal layer.
4 more elements
Dependencies are inferred from the claim text.