Flash memory device having multi-stack structure and channel separation method thereof

A flash memory device comprising:

• a first word line connected with a first memory cell;
• a second word line connected with a second memory cell on the first memory cell;
• and
• a third word line connected with a third memory cell between the first memory cell and the second memory cell,
• wherein the first memory cell, the second memory cell and the third memory cell share a channel, and
• wherein regions of the channel are classified depending on a location of the second word line, and a channel separation voltage or a channel connection voltage is provided to the third word line depending on a number of program loops, which is differently determined depending on the regions.

A channel separation method of a flash memory device which includes a first stack including first memory cells, and a second stack including second memory cells provided on the first stack, the channel separation method comprising:

• defining a plurality of regions depending on channel diameters of the second memory cells;
• determining whether a program loop associated with a memory cell selected from the second memory cells reaches a specific program loop;
• and
• controlling channel connection or channel separation between the first stack and the second stack depending on a number of program loops,
• wherein the controlling the channel connection or the channel separation is differently determined for each of the plurality of regions.