US 2023/0145089 A1 · VERTICAL EDGE BLOCKING (VEB) TECHNIQUE FOR INCREASING PATTERNING PROCESS MARGIN

Abstract

Embodiments disclosed herein include semiconductor devices and methods of forming such semiconductor devices. In an embodiment, a method of fabricating a semiconductor device comprises, forming a first grating of parallel first lines, forming a second grating of parallel second lines, wherein the second lines are substantially orthogonal to the first lines, and wherein the first lines and second lines define a plurality of first openings, disposing a conformal mask layer over the first lines and the second lines, wherein the conformal mask layer partially fills the first openings and defines a second opening within each of the first openings, disposing a hardmask over the conformal mask layer, wherein the hardmask fills the second openings, patterning third openings into the hardmask, wherein the third openings clear the hardmask from at least one of the second openings, and removing the mask layer proximate to cleared second openings to clear first openings.

Claims18

Dependent claims

A semiconductor device, comprising:

a first interlayer dielectric (ILD);
a grid of source/drain (S/D) contacts and gate contacts in the first ILD, wherein the gate contacts and the S/D contacts are arranged in an alternating pattern, and wherein top surfaces of the gate contacts are below top surfaces of the S/D contacts so that an opening defined by sidewall surfaces of the first ILD is positioned over each of the gate contacts;
a mask layer partially filling a first opening over a first gate contact;
and
a fill metal filling a second opening over a second gate contact that is adjacent to the first gate contact.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application

18/096,351Filed 12 Jan 2023

Priority

7 Jun 2019

Published

11 May 2023

Term ends

Not estimatedThe source records don’t support an estimate.

Classification11 codes

H10W 20/069
Of conductive parts of the interconnections: by forming self-aligned vias or self-aligned contact plugs
H10W 20/089
By forming openings in the dielectric parts: using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning
H10D 64/251
Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes: source or drain…
H10D 64/411
Gate electrodes for field-effect devices: for FETs

Vertical edge blocking (veb) technique for increasing patterning process margin

Life of this patent

Vertical edge blocking (veb) technique for increasing patterning process margin

Life of this patent

Abstract

Claims18