Fpga implementation device and method for fblms algorithm based on block floating point

An FPGA implementation device for an FBLMS algorithm based on block floating point, comprising an input caching and converting module, a filtering module, an error calculating and output caching module, a weight adjustment amount calculating module and a weight updating and storing module, in which

• the input caching and converting module is suitable for blocking, caching, and reassembling an input time domain reference signal according to an overlap-save method, converting the blocked, cached and reassembled signal from a fixed point system to a block floating point system, and then performing fast Fourier transform (FFT) and caching mantissa, to obtain a frequency domain reference signal with a block floating point system, and outputting the frequency domain reference signal with block floating point system to the filtering module and the weight adjustment amount calculating module;
• the filtering module is suitable for performing complex multiplication on the frequency domain reference signal with block floating point system and a frequency domain block weight sent by the weight updating and storing module to obtain a complex multiplication result, determining a significant bit according to a maximum absolute value in the complex multiplication result, and then performing dynamic truncation to obtain a filtered frequency domain reference signal, and sending the filtered frequency domain reference signal to the error calculating and output caching module;
• the error calculating and output caching module is configured to perform inverse fast Fourier transform (IFFT) on the filtered frequency domain reference signal;
• the error calculating and output caching module is further configured to perform ping pong cache on an input target signal and convert the cached target signal to a block floating point system;
• the error calculating and output caching module is further configured to calculate a difference between the target signal converted to block floating point system and the reference signal on which IFFT is performed to obtain an error signal;
• and the error calculating and output caching module is further configured to divide the error signal into two same signals, where one of which is sent to the weight adjustment amount calculating module, and the other is converted to fixed point system, and then is subjected to cyclic caching, to obtain output continuously cancellation result signals;
• the weight adjustment amount calculating module is configured to obtain an adjustment amount of frequency domain block weight with block floating point system based on the error signal and the frequency domain reference signal with block floating point system;
• and
• the weight updating and storing module is configured to convert the adjustment amount of frequency domain block weight with block floating point system to an extended bit width fixed point system, and then updates and stores the updated frequency domain block weight on a block basis;
• and the weight updating and storing module is further configured to perform dynamic truncation on the updated frequency domain block weight, and then convert a dynamic truncation result to block floating point system, and send the dynamic truncation result to the filtering module.