Semiconductor package

A semiconductor package comprising:

• a package substrate comprising a first chip mounting area, a second chip mounting area, and a third chip mounting area spaced apart from one another in a first direction;
• a stiffener on the package substrate, the stiffener forming a first heat dissipation space on the first chip mounting area, a second heat dissipation space on the second chip mounting area, and a third heat dissipation space on the third chip mounting area;
• at least one first semiconductor chip on the first chip mounting area and in the first heat dissipation space;
• at least one second semiconductor chip on the second chip mounting area and in the second heat dissipation space;
• and
• at least one third semiconductor chip on the third chip mounting area and in the third heat dissipation space,
• wherein the stiffener comprises:
• a first stiffener comprising a first support pillar on a first corner area of the package substrate, a second support pillar on a second corner area of the package substrate, and a first bridge extending from the first support pillar to the second support pillar in a second direction perpendicular to the first direction and between the first chip mounting area and the second chip mounting area;
• and
• a second stiffener mounted on the package substrate between the second chip mounting area and the third chip mounting area, the second stiffener comprising a third support pillar on a third corner area of the package substrate, a fourth support pillar on a fourth corner area of the package substrate, and a second bridge extending from the third support pillar to the fourth support pillar in the second direction and between the second chip mounting area and the third chip mounting area,
• wherein the first heat dissipation space, the second heat dissipation space, and the third heat dissipation space are spaced apart from one another, and
• wherein the first heat dissipation space, the second heat dissipation space, and the third heat dissipation space are exposed to the outside of the stiffener in a third direction.

A semiconductor package comprising:

• a package substrate comprising a first chip mounting area, a second chip mounting area, and a third chip mounting area spaced apart from one another in a first direction, the second chip mounting area comprising a first sub-mounting area, a second sub-mounting area, and a third sub-mounting area spaced apart from one another in a second direction perpendicular to the first direction;
• a first memory chip on the first chip mounting area;
• a first PMIC chip on the first sub-mounting area;
• a system on chip (SOC) on the second sub-mounting area;
• a second PMIC chip on the third sub-mounting area;
• a second memory chip on the third chip mounting area;
• a first stiffener on the package substrate between the first chip mounting area and the second chip mounting area, the first stiffener comprising a first support pillar on a first corner area of the package substrate, a second support pillar on a second corner area of the package substrate, and a first bridge extending from the first support pillar to the second support pillar in the second direction and between the first chip mounting area and the second chip mounting area;
• a second stiffener on the package substrate between the second chip mounting area and the third chip mounting area, the second stiffener comprising a third support pillar on a third corner area of the package substrate, a fourth support pillar on a fourth corner area of the package substrate, and a second bridge extending from the third support pillar to the fourth support pillar in the second direction and between the second chip mounting area and the third chip mounting area;
• a first interstiffener bridge extending from the first bridge to the second bridge in the first direction and between the first sub-mounting area and the second sub-mounting area;
• and
• a second interstiffener bridge extending from the first bridge to the second bridge in the first direction and between the second sub-mounting area and the third sub-mounting area, and
• wherein side walls of the SOC are adjacent to the first bridge, the second bridge, the first interstiffener bridge, and the second interstiffener bridge.