Method and system for providing configuration data to a field-programmable gate array via multiple protocol modes

A configurable semiconductor device able to process information, comprising:

• a storage configured to store at least one version of configuration data provided by a user to perform user-defined logic functions;
• a selectable multi-mode channel (“SMC”) coupled to the storage and configured to transmit information via one of multiple transmission modes;
• and
• a programmable integrated circuit (“PIC”), having configurable logic blocks (“LBs”) and a configuration memory for facilitating user-defined logic functions, configured to include a multi-mode controller (“MMC”) coupled to the SMC for facilitating optional election between multiple modes in response to mode information carried by at least a portion of address bits of the SMC.

A method for providing configuration data to a programmable logic device (“PLD”) via a selectable multi-mode channel, the method comprising:

• detecting an Improved Inter-Integrated Circuit (“I3C”) mode in accordance with at least a portion of address bits on a serial data line (“SDA”) coupling a PLD to an external storage;
• configuring a multi-mode controller (“MMC”) to facilitate the I3C mode for processing data from the SDA in accordance with I3C clock cycles carried over a serial clock line (“SCL”) coupling the PLD to the external storage;
• and
• transmitting configuration data from the external storage to a configuration storage in the PLD via the SDA in response to the clock cycles.

A method for providing configuration data to a programmable logic device (“PLD”) via a selectable multi-mode channel, the method comprising:

• detecting Inter-Integrated Circuit (“I2C”) mode in accordance with at least a portion of address bits on a serial data line (“SDA”) coupling an FPGA to an external device;
• configuring a multi-mode controller (“MMC”) to facilitate the I2C mode for processing data from the SDA in accordance with I2C clock cycles carried over a serial clock line (“SCL”) coupling the PLD to the external storage;
• and
• transmitting configuration data from the external storage to a configuration storage in the PLD via the SDA in response to the clock cycles.