Integrated circuit devices including stacked transistors and methods of forming the same

An integrated circuit device comprising:

• a stacked structure comprising:
• an upper transistor on a substrate, the upper transistor comprising:
• an upper gate electrode comprising side surfaces that are spaced apart from each other in a first horizontal direction;
• and
• an upper active region in the upper gate electrode, wherein the upper active region comprises an inner layer and an outer layer enclosing the inner layer when viewed in a cross-section taken along a second horizontal direction that is different from the first horizontal direction, and the inner layer and the outer layer comprise different materials;
• and
• a lower transistor between the substrate and the upper transistor, the lower transistor comprising:
• a lower gate electrode;
• and
• a lower active region in the lower gate electrode.

A method of forming an integrated circuit device, the method comprising:

• providing a preliminary structure on a substrate, the preliminary structure comprising:
• an insulating layer including an opening;
• a preliminary upper active region in the opening;
• and
• a lower active region that is in the opening and is between the substrate and the preliminary upper active region;
• and
• forming an inner layer by etching the preliminary upper active region;
• forming an outer layer on the inner layer;
• forming a lower gate electrode in the opening on the lower active region;
• and
• forming an upper gate electrode in the opening on the outer layer.