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US 2023/0141943 A1Published application
Transceiver for providing high voltages for erase or program operations in a non-volatile memory system
AssigneeSilicon Storage Technology, Inc.
InventorsHieu Van Tran, Anh Ly, Kha Nguyen, Hien Pham, Duc Nguyen
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Abstract
Numerous embodiments of a transceiver for providing high voltages for use during erase or program operations in a non-volatile memory system are disclosed. In one embodiment, a transceiver comprises a PMOS transistor and a native NMOS transistor. In another embodiment, a transceiver comprises a PMOS transistor, an NMOS transistor, and a native NMOS transistor.
Claims12
A transceiver for a non-volatile memory system, comprising:
- a PMOS transistor comprising a first terminal coupled to a first node, a second terminal, and a gate;
- and
- a native NMOS transistor comprising a first terminal coupled to the second terminal of the PMOS transistor, a second terminal coupled to a second node, and a gate;
- wherein the transceiver can provide a first high voltage on one of the first node and the second node in response to receiving a second high voltage on the other of the first node and the second node.
1 more element
A transceiver for a non-volatile memory, comprising:
- a PMOS transistor comprising a first terminal, a second terminal, and a gate;
- an NMOS transistor comprising a first terminal coupled to the first terminal of the PMOS transistor coupled to a first node, a second terminal, and a gate;
- and
- a native NMOS transistor comprising a first terminal coupled to the second terminal of the PMOS transistor and the second terminal of the NMOS transistor, a second terminal coupled to a second node, and a gate;
- wherein the transceiver selectively provides a first high voltage on one of the first node and the second node in response to receiving a second high voltage on the other of the first node and the second node.
2 more elements
Dependencies are inferred from the claim text.