Secure processor, operating method thereof, and storage device including same
AssigneeSamsung Electronics Co., Ltd.
InventorEun Young JUNG
Life of this patent
Estimating the term…
Abstract
Provided are a secure processor, an operating method thereof, and a storage device including the secure processor. Provided is a secure processor including a secure core including a vector table register containing boot-up address information, and a vector table register controller configured to communicate with the secure core, wherein the vector table register controller includes a lock controller configured to lock the vector table register and a count register configured to store a lock count value that is the number of times the boot-up address information of the vector table register is updated.
Claims20
A secure processor, comprising:
- a secure core including a vector table register for boot-up address information;
- and
- a vector table register controller configured to communicate with the secure core, the vector table register controller including:
- a lock controller configured to lock the vector table register;
- and
- a count register configured to store a lock count value that is a number of times the boot-up address information of the vector table register is updated.
A storage device, comprising:
- a storage controller configured to control an operation of the storage device, the storage controller including a secure processor that includes:
- a secure core including a vector table register containing boot-up address information;
- and
- a vector table register controller configured to communicate with the secure core,
- wherein the vector table register controller includes:
- a lock controller configured to lock the vector table register;
- and
- a count register configured to store a lock count value that is a number of times the boot-up address information of the vector table register is updated.
A method of operating a secure processor, comprising:
- storing boot-up address information in a vector table register inside a secure core;
- and
- communicating with the secure core through a vector table register controller,
- wherein the vector table register controller locks the vector table register through a lock controller and stores a lock count value, which is a number of times the boot-up address information of the vector table register is updated, in a count register.
Dependencies are inferred from the claim text.