Cladding and condensation for strained semiconductor nanoribbons

An electronic device, comprising:

• a chip package comprising one or more dies, at least one of the one or more dies comprising
• a semiconductor device having one or more semiconductor nanoribbons extending between a source region and a drain region;
• a first spacer structure around first ends of the one or more semiconductor nanoribbons;
• a second spacer structure around second ends of the one or more semiconductor nanoribbons;
• and
• a gate structure around the one or more semiconductor nanoribbons and between the first and second spacer structures;
• wherein at least one nanoribbon of the one or more semiconductor nanoribbons includes a first region at one end of the nanoribbon having substantially no germanium (Ge), a second region at the other end of the nanoribbon having substantially no germanium, and a third region between the first and second regions, wherein an entirety of the third region has a non-zero Ge concentration and the third region extends through an entire thickness of the nanoribbon.

An integrated circuit comprising:

• a semiconductor device having a plurality of semiconductor nanoribbons extending between a source region and a drain region;
• a first spacer structure around first ends of the plurality of semiconductor nanoribbons;
• a second spacer structure around second ends of the plurality of semiconductor nanoribbons;
• and
• a gate structure around the semiconductor nanoribbons and between the first and second spacer structures;
• wherein at least one nanoribbon of the plurality of semiconductor nanoribbons includes a first region at one end of the nanoribbon having substantially no tin (Sn), a second region at the other end of the nanoribbon having substantially no tin, and a third region between the first and second regions, wherein an entirety of the third region has a non-zero tin concentration and the third region extends through an entire thickness of the at least one nanoribbon.