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US 2023/0128025 A1Published application
Systems and methods for decomposed digital filter
AssigneeIntel Corporation
InventorVolker Mauer
Life of this patent
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Abstract
Circuitry, systems, and methods are provided for an integrated circuit that includes digital filter circuitry. The digital filtering circuitry includes a first partial filter that includes a first number of taps corresponding to coefficients of a first bit depth and a second partial filter that includes a second number of taps corresponding to coefficients of a second bit depth.
Claims20
An integrated circuit comprising:
- digital filter circuitry comprising:
- a first partial filter comprising a first number of taps corresponding to coefficients of a first bit depth;
- and
- a second partial filter comprising a second number of taps corresponding to coefficients of a second bit depth.
1 more element
An integrated circuit comprising:
- a finite impulse response filter of a higher bit-width formed from multiple sub-filters of a lower bit-width, wherein the multiple sub-filters comprise:
- a first sub-filter, wherein the first sub-filter comprises a first plurality of coefficients with a first bit-width, and
- a second sub-filter, wherein the second sub-filter comprises a second plurality of coefficients with a second bit-width.
Digital processing circuitry, comprising:
- a first sub-filter comprising a first number of taps corresponding to coefficients of a first bit depth and configurable to receive a first portion of a sample to generate a first output;
- a second sub-filter comprising a second number of taps corresponding to coefficients of a second bit depth and configurable to receive a second portion of a sample to generate a second output;
- and
- a third sub-filter comprising a third number of taps corresponding to coefficients of a third bit depth and configurable to receive a third portion of a sample to generate a third output.
1 more element
Dependencies are inferred from the claim text.