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US 2023/0111844 A1Published application
Memory device including partial pages in memory blocks
AssigneeSK hynix Inc.
InventorsSung Lae OH, Jin Ho KIM, Sang Hyun SUNG, Hyun Soo SHIN
Life of this patent
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Abstract
A memory device includes a plurality of bit lines extending in a first direction and arranged in a second direction; and a cell region including a plane which is coupled to the plurality of bit lines, wherein the plane is divided into a plurality of memory groups each including a plurality of partial pages to be disposed in a plurality of rows in the first direction.
Claims19
A memory device comprising:
- a plurality of bit lines extending in a first direction and arranged in a second direction;
- and
- a cell region that includes a plane and that is coupled to the plurality of bit lines,
- wherein the plane is divided into a plurality of memory groups, each including a plurality of partial pages, that are disposed in a plurality of rows arranged in the first direction.
1 more element
A memory device comprising:
- a plurality of bit lines extending in a first direction and arranged in a second direction;
- and
- a cell region including a plurality of memory blocks that are coupled to the plurality of bit lines,
- wherein each memory block is divided into a plurality of sub-blocks each including a plurality of partial pages that are disposed in a plurality of rows arranged in the first direction.
1 more element
A memory device comprising:
- a cell region included in a first wafer, and including a plurality of memory blocks, which are coupled to a plurality of bit lines that extend in a first direction and that are arranged in a second direction;
- a pass transistor circuit, included in the first wafer, that is configured to transfer an operating voltage to the plurality of memory blocks in response to a block selection signal;
- and
- a block switch circuit included in a second wafer, which overlaps with the first wafer in a vertical direction, that is configured to provide the block selection signal to the pass transistor circuit,
- wherein each memory block is divided into a plurality of sub-blocks each including a plurality of partial pages that are disposed in a plurality of rows arranged in the first direction.
2 more elements
Dependencies are inferred from the claim text.