In-memory associative processing system

An apparatus, comprising:

• a memory die comprising a plurality of tiles each comprising a plurality of planes, wherein each plane comprises a respective array of content-addressable memory cells;
• logic coupled with the memory die and configured to:
• receive, from a host device, signaling that indicates a set of instructions indicating a vector as an operand for a computational operation, the vector comprising a plurality of elements each having a respective bit length;
• write data representative of a first set of contiguous bits of at least one element of the plurality of elements to a first plane of a tile and data representative of a second set of contiguous bits of the at least one element to a second plane of the tile;
• and
• perform, using associative processing, the computational operation based at least in part on writing the data representative of the first set of contiguous bits to the first plane and based at least in part on writing the data representative of the second set of contiguous bits to the second plane.

An apparatus, comprising:

• a memory die comprising a plurality of tiles each comprising a plurality of planes, wherein each plane comprises a respective array of content-addressable memory cells;
• logic coupled with the memory die and configured to:
• receive, from a host device, signaling that indicates a set of instructions indicating a vector as an operand for a computational operation, the vector comprising a plurality of elements each having a respective bit length;
• write data representative of a first set of contiguous bits of at least one element of the plurality of elements to a first plane of a first tile and data representative of a second set of contiguous bits of the at least one element to a second plane of a second tile;
• and
• perform, using associative processing, the computational operation based at least in part on writing the data representative of the first set of contiguous bits to the first plane and based at least in part on writing the data representative of the second set of contiguous bits to the second plane.

An apparatus, comprising:

• a host device configured to transmit signaling that indicates a set of instructions indicating a vector as an operand for a computational operation, the vector comprising a plurality of elements each having a respective bit length;
• a device coupled with the host device and configured to perform associative processing, the device comprising a plurality of tiles that each comprise a plurality of planes, wherein each plane comprises a respective array of content-addressable memory cells;
• logic coupled with the device and configured to:
• receive the signaling that indicates the set of instructions from the host device;
• select between a first vector mapping scheme and a second vector mapping scheme for writing vectors to planes of the device;
• write, based at least in part on the selected vector mapping scheme, data representative of a first set of contiguous bits of an element of the vector to a first plane and data representative of a second set of contiguous bits of the element to a second plane;
• and
• perform, based at least in writing the data representative of the first and second sets of contiguous bits, the computational operation using associative processing.

A method, comprising:

• receiving, at an apparatus, signaling that indicates a set of instructions indicating a first vector and a second vector as operands for a computational operation;
• selecting, from a set of vector mapping schemes, a vector mapping scheme for performing the computational operation using associative processing;
• and
• writing data representative of the first vector and data representative of the second vector to a set of planes each comprising an array of content-addressable memory cells based at least in part on the selected vector mapping scheme.