Metal interconnect structures and methods of fabricating the same

An interconnect structure for an integrated circuit device, comprising:

• a first metal interconnect feature having a hillock;
• a first dielectric layer over the first metal interconnect feature, the first dielectric layer having a localized elevated region overlying the hillock;
• a second dielectric layer over the first dielectric layer;
• a third dielectric layer over the second dielectric layer;
• a fourth dielectric layer over the third dielectric layer;
• and
• a second metal interconnect feature having a planar bottom surface overlying the localized elevated region of the first dielectric layer and the hillock of the first metal interconnect feature, the second metal interconnect feature laterally surrounded by the fourth dielectric layer, the third dielectric layer, and a portion of the second dielectric layer, and the second dielectric layer and the first dielectric layer extend continuously between the first metal interconnect feature and the planar bottom surface of the second metal interconnect feature.

An interconnect structure for an integrated circuit device, comprising:

• a first metal interconnect feature;
• a first dielectric layer over the first metal interconnect feature;
• a second dielectric layer over the first dielectric layer;
• a third dielectric layer over the second dielectric layer;
• a fourth dielectric layer over the third dielectric layer;
• and
• a third metal interconnect feature above the first metal interconnect feature and electrically connected to the first metal interconnect feature by a conductive via extending through the first dielectric layer and the second dielectric layer, the third metal interconnect feature laterally surrounded by the fourth dielectric layer, the third dielectric layer, and a portion of the second dielectric layer, wherein:
• the third metal interconnect feature comprises a barrier layer and a metallic fill material, a portion of the barrier layer extends between the metallic fill material and an upper surface of the conductive via, and a vertical offset distance between a bottom surface of the third dielectric layer and an upper surface of the portion of the barrier layer extending over the upper surface of the conductive via is at least about 10% of a total thickness of the second dielectric layer.