Memory devices using a dynamic latch to provide multiple bias voltages

A method of operating a memory device comprising a sense amplifier (SA) latch selectively connected to a sense node;

• a dynamic latch connected to the SA latch and selectively connected to the sense node, the dynamic latch including a latch transistor and one or more set transistors;
• a sense line comprising the sense node and selectively connected to the SA latch, the dynamic latch, and a bit line that is coupled to a string of series-connected memory cells, and wherein the method of operating the memory device comprises performing a plurality of operations comprising:
• causing a pre-program verify voltage to provide a boost to the sense node;
• and
• in response to detecting a high bit value stored in the SA latch, causing a set voltage to turn on the one or more set transistors of the dynamic latch so that one of a first bias voltage or a second bias voltage is stored at the latch transistor, wherein:
• the first bias voltage is useable for slow programming of a selected memory cell of the string of series-connected memory cells;
• and
• the second bias voltage is useable for fast programming of the selected memory cell of the string of series-connected memory cells, wherein the fast programming is faster than the slow programming.

A memory device comprising:

• a sense amplifier (SA) latch selectively connected to a sense node;
• a dynamic latch connected to the SA latch and selectively connected to the sense node;
• a sense line comprising the sense node and selectively connected to the SA latch, the dynamic latch, and a bit line, wherein the bit line is coupled to a string of series-connected memory cells;
• and
• control logic coupled to the SA latch and the dynamic latch, wherein to program a bit line bias, the control logic is to perform operations comprising:
• causing a program pulse to be sent down the bit line to program a selected memory cell of the string of series-connected memory cells;
• causing an output voltage of the SA latch to be sent to the sense node, wherein the output voltage of the SA latch is a common collector voltage (Vcc);
• causing a first voltage of the sense node to be selectively discharged by the dynamic latch to generate an updated first voltage at the sense node;
• and
• causing a bit value stored in the SA latch to be selectively flipped depending on a value of the updated first voltage of the sense node.