Semiconductor package

A semiconductor package, comprising:

• a redistribution substrate having a first surface and a second surface opposite to the first surface;
• a first semiconductor chip on the first surface of the redistribution substrate;
• a second semiconductor chip above the first semiconductor chip, a portion of the second semiconductor chip vertically overlapping the first semiconductor chip;
• a plurality of connection terminals between the first semiconductor chip and the redistribution substrate;
• a plurality of external connection members below the second semiconductor chip;
• and
• a plurality of conductive pillars that vertically extends from the redistribution substrate toward the external connection members,
• wherein the second semiconductor chip includes:
• a semiconductor substrate;
• and
• a device layer, a wiring layer, and a redistribution layer sequentially stacked on the semiconductor substrate,
• wherein the wiring layer includes:
• a plurality of sequentially stacked intermetallic dielectric layers;
• a plurality of wiring lines between the intermetallic dielectric layers;
• and
• a conductive pad connected to an uppermost one of the wiring lines,
• wherein the redistribution layer includes:
• a first redistribution dielectric layer that covers the wiring layer;
• a first redistribution pattern that penetrates the first redistribution dielectric layer to connect with the conductive pad and extends onto the first redistribution dielectric layer;
• and
• a second redistribution dielectric layer that covers the first redistribution pattern and the first redistribution dielectric layer,
• wherein each of the external connection members includes:
• a conductive bump pattern in contact with the first redistribution pattern;
• and
• a solder pattern on the conductive bump pattern,
• wherein a pitch between the connection terminals is less than a pitch between the external connection members, and
• wherein a maximum width of each of the connection terminals is less than a maximum width of each of the external connection members.

A semiconductor package, comprising:

• a redistribution substrate having a first surface and a second surface opposite to the first surface, the redistribution substrate including
• a first redistribution dielectric layer, and
• a first redistribution pattern, a second redistribution pattern, and a third redistribution pattern sequentially provided in a direction from the second surface toward the first surface of the redistribution substrate;
• a first semiconductor chip on the first surface of the redistribution substrate;
• a second semiconductor chip above the first semiconductor chip, a portion of the second semiconductor chip vertically overlaps the first semiconductor chip;
• a plurality of connection terminals between the first semiconductor chip and the redistribution substrate;
• a plurality of external connection members on the second semiconductor chip, each of the external connection members including a conductive bump pattern and a solder pattern on the conductive bump pattern;
• a plurality of conductive pillars that electrically connect the solder pattern to the redistribution substrate;
• a molding layer that covers the first semiconductor chip and the second semiconductor chip;
• and
• a plurality of external terminals on the second surface of the redistribution substrate,
• wherein the second semiconductor chip includes:
• a semiconductor substrate;
• and
• a device layer, a wiring layer, and a redistribution layer sequentially stacked on the semiconductor substrate,
• wherein the wiring layer includes:
• a plurality of sequentially stacked intermetallic dielectric layers;
• a plurality of wiring lines between the intermetallic dielectric layers;
• and
• a conductive pad connected to an uppermost one of the wiring lines,
• wherein the redistribution layer includes:
• a second redistribution dielectric layer that covers the wiring layer;
• a fourth redistribution pattern that penetrates the second redistribution dielectric layer to connect with the conductive pad and extends onto the second redistribution dielectric layer;
• and
• a third redistribution dielectric layer that covers the fourth redistribution pattern and the second redistribution dielectric layer,
• wherein the fourth redistribution pattern includes:
• a contact part that penetrates the second redistribution dielectric layer to connect with the conductive pad;
• a pad part on the second redistribution dielectric layer;
• and
• a line part that connects the contact part to the pad part,
• wherein the pad part is in contact with the conductive bump pattern,
• wherein each of the first, second, and third redistribution patterns includes:
• a wire part that extends in a direction parallel to the first surface of the redistribution substrate;
• and
• a via part that protrudes from the wire part in a direction toward the second surface of the redistribution substrate,
• wherein a width of the via part decreases in a direction from the first surface toward the second surface of the redistribution substrate, and
• wherein a vertical distance between the semiconductor substrate and the conductive pillars is less than a vertical distance between the first semiconductor chip and the external terminals.