US 2023/0069423 A1 · MEMORY DEVICE AND MEMORY SYSTEM HAVING THE MEMORY DEVICE

Abstract

Provided herein may be a memory device and a memory system having the memory device. The memory system includes a memory device including a plurality of memory blocks, each including chunk blocks, and page buffer blocks respectively coupled to the chunk blocks, and a memory controller configured to, based on chunk block status information indicating whether each of the chunk blocks is one of a pass chunk block and a bad chunk block, control the memory device to perform an operation corresponding to a command on merged pass chunk blocks obtained by merging pass chunk blocks coupled to different page buffer blocks among pass chunk blocks included in memory blocks, each of the memory blocks including both the pass chunk block and the bad chunk block.

Claims19

Dependent claims

A memory system, comprising:

a memory device including a plurality of memory blocks, each including chunk blocks, and page buffer blocks respectively coupled to the chunk blocks;
and
a memory controller configured to, based on chunk block status information indicating whether each of the chunk blocks is one of a pass chunk block and a bad chunk block, control the memory device to perform an operation corresponding to a command on merged pass chunk blocks obtained by merging pass chunk blocks coupled to different page buffer blocks among pass chunk blocks included in memory blocks, each of the memory blocks including both the pass chunk block and the bad chunk block.

A memory device, comprising:

a plurality of memory blocks, each including chunk blocks, each of the chunk blocks comprising one of a pass chunk block and a bad chunk block;
page buffer blocks coupled to the chunk blocks, respectively;
an address decoder configured to apply an operating voltage to a memory block selected from among the plurality of memory blocks;
a block register configured to store a block address corresponding to merged pass chunk blocks obtained by merging pass chunk blocks coupled to different page buffer blocks, among pass chunk blocks included in memory blocks, each including both the pass chunk block and the bad chunk block;
and
an operation controller configured to, when a command and the block address are received from a memory controller, control the address decoder to apply an operating voltage corresponding to the command to the merged pass chunk blocks selected by the block address.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application

17/580,222Filed 20 Jan 2022

Priority

KR 10-2021-011513530 Aug 2021

Published

2 Mar 2023

Term ends

Not estimatedThe source records don’t support an estimate.

Classification10 codes

G06F 3/0659
Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices: command handling…
G06F 3/0679
Single storage device: non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
G06F 3/0604
Specifically adapted to achieve a particular effect: improving or facilitating administration, e.g. storage management
G06F 3/0619
Improving the reliability of storage systems: in relation to data integrity, e.g. data losses, bit errors

Memory device and memory system having the memory device

Life of this patent

Memory device and memory system having the memory device

Life of this patent

Abstract

Claims19