Sub-block programming mode with multi-tier block

A method, comprising:

• in response to a program command for a selected sub-block of a block, determining a program or erase status of unselected sub-blocks of the block, each sub-block of the block comprising memory cells connected to word lines in a respective tier of a plurality of tiers of the block, the memory cells are arranged in NAND strings and the block comprises a drain side and a source side;
• determining whether to pre-charge channels of the NAND strings from the drain side or the source side of the block based on the program or erase status of the unselected sub-blocks;
• applying a plurality of program pulses to a selected word line of the selected sub-block in a program operation;
• and
• pre-charging the channels of the NAND strings from the drain side or the source side of the block before each program pulse based on the program or erase status of the unselected sub-blocks.

An apparatus, comprising:

• a block comprising memory cells connected to word lines in a plurality of sub-blocks, each sub-block is in a respective tier of a plurality of tiers of the block, the block comprises a drain side and a source side, the plurality of sub-blocks comprise a drain-side sub-block adjacent to the drain side of the block and a source-side sub-block adjacent to the source side of the block, and the memory cells are arranged in NAND strings which extend from the drain side to the source side of the block;
• and
• a control circuit, the control circuit:
• to erase memory cells in the drain-side sub-block, is configured to charge up channels of the NAND strings from the drain side of the block while inhibiting erase of memory cells in the source-side sub-block;
• to erase memory cells in the source-side sub-block, is configured to charge up the channels of the NAND strings from the source side of the block while inhibiting erase of memory cells in the drain-side sub-block;
• to reserve the source-side sub-block for programming in an N1 bit per cell mode;
• and
• to reserve the drain-side sub-block for programming in an N2>N1 bit per cell mode.