Low latency host processor to coherent device interaction

A non-transitory computer-readable medium comprising instructions that are executable in an I/O device controller that is connected to a processor via a coherence interconnect, wherein the I/O device controller executes the instructions to carry out the steps of:

• detecting that the processor updated a first cache line, wherein the first cache line is stored in a memory accessible by the processor and the I/O device controller and retrieved into a cache of the processor;
• after the first cache line, as updated by the processor, is written to the memory, retrieving a command from the first cache line and executing the command;
• and
• writing a result of executing the command to a second cache line stored in the memory.

A computer system comprising:

• a processor;
• and
• an I/O device controller communicating with the processor via a coherence interconnect and according to a cache coherence protocol, wherein the I/O device controller is configured to:
• detect that the processor updated a first cache line, wherein the first cache line is stored in a memory accessible by the processor and the I/O device controller and retrieved into a cache of the processor;
• after the first cache line, as updated by the processor, is written to the memory, retrieve a command from the first cache line and execute the command;
• and
• write a result of executing the command to a second cache line stored in the memory.