Video decoder with hardware shared between different processing circuits and associated video decoding method

Abstract

A video decoder has a plurality of processing circuits, including a first processing circuit and a second processing circuit. The first processing circuit applies a first decoding process to a current coding block according to reconstructed neighbor samples, and has a local neighbor buffer for buffering the reconstructed neighbor samples used by the first decoding process. The second processing circuit applies a second decoding process to the current coding block according to at least a portion of the reconstructed neighbor samples retrieved from the local neighbor buffer, wherein the second decoding process is different from the first decoding process.

Dependencies are inferred from the claim text.