US 2023/0068950 A1 · LEAKAGE INSENSITIVE TRANSISTOR CIRCUITS

Abstract

A leakage insensitive transistor includes a substrate, a source region, a drain region, a channel region between the source region and drain region, a gate dielectric on the channel region, first and second electrodes on the gate dielectric, and third and fourth electrodes on the substrate. The leakage insensitive transistor may be operated by applying a first logic signal to the first electrode, floating the second electrode of the FET, applying a second logic signal opposite the first logic signal to the third electrode, and floating the fourth electrode. A logic circuit may include multiple leakage insensitive transistors.

Claims22

Dependent claims

An apparatus comprising:

a substrate;
a source region;
a drain region;
a channel region between the source region and drain region;
a gate dielectric on the channel region;
first and second electrodes on the gate dielectric;
and
third and fourth electrodes on the substrate.

5 more elements

A logic circuit comprising:

a first field-effect transistor (FET) comprising first and second electrodes on a gate dielectric of the FET, third and fourth electrodes on the substrate of the FET, a fifth electrode on a source region of the FET, and a sixth electrode on a drain region of the FET;
a second FET comprising first and second electrodes on a gate dielectric of the FET, third and fourth electrodes on the substrate of the FET, a fifth electrode on a source region of the FET, and a sixth electrode on a drain region of the FET;
a third FET comprising first and second electrodes on a gate dielectric of the FET, third and fourth electrodes on the substrate of the FET, a fifth electrode on a source region of the FET, and a sixth electrode on a drain region of the FET;
and
a fourth FET comprising first and second electrodes on a gate dielectric of the FET, third and fourth electrodes on the substrate of the FET, a fifth electrode on a source region of the FET, and a sixth electrode on a drain region of the FET;
wherein:
the first electrode of the first FET, the first electrode of the second FET, the first electrode of the third FET, and the first electrode of the fourth FET are connected;
the second electrode of the first FET, the second electrode of the second FET, the second electrode of the third FET, and the second electrode of the fourth FET are connected;
the third electrode of the first FET, the third electrode of the second FET, the third electrode of the third FET, and the third electrode of the fourth FET are connected;
and
the fourth electrode of the first FET, the fourth electrode of the second FET, the fourth electrode of the third FET, and the fourth electrode of the fourth FET are connected.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application

17/405,953Filed 18 Aug 2021

Published

2 Mar 2023

Term ends

Not estimatedThe source records don’t support an estimate.

Classification8 codes

H10D 30/611
Insulated-gate field-effect transistors [IGFET]: having multiple independently-addressable gate electrodes influencing the same channel
H10D 30/615
Having multiple independently-addressable gate electrodes influencing the same channel: comprising a MOS gate electrode and at least one non-MOS…
H03K 19/0013
Arrangements for reducing power consumption: in field effect transistor circuits
H10D 30/6215
Fin field-effect transistors [FinFET]: having multiple independently-addressable gate electrodes

Leakage insensitive transistor circuits

Life of this patent

Leakage insensitive transistor circuits

Life of this patent

Abstract

Claims22