Stacked transistor arrangement and process of manufacture thereof

A stacked transistor arrangement comprising:

• a first transistor chip having one or more source electrodes on a first side of the first transistor chip, one or more drain electrodes on a second side of the first transistor chip, the second side of the first transistor chip being opposite the first side of the first transistor chip and the first transistor chip having one or more gate electrodes;
• a second transistor chip having one or more source electrodes on a first side of the second transistor chip, one or more drain electrodes on a second side of the second transistor chip, the second side of the second transistor chip being opposite the first side of the second transistor chip and the first transistor chip having one or more gate electrodes, wherein the second side of the first transistor chip is positioned adjacent to the second side of the first transistor chip and wherein drain electrodes of the first transistor chip and drain electrodes of the second transistor chip are coupled together by a conductive layer positioned between the first transistor chip and the second transistor chip;
• and
• a lead frame, wherein the source electrodes of the first side of the first transistor chip and the source electrodes of the first side of the second transistor chip are coupled to the lead frame by one or more connectors selected from the group consisting of:
• bond wires;
• and solder bumps.

A method of manufacture for a stacked transistor arrangement comprising steps of:

• providing a first transistor chip having one or more source electrodes on a first side of the first transistor chip, one or more drain electrodes on a second side of the first transistor chip, the second side of the first transistor chip being opposite the first side of the first transistor chip and the first transistor chip having one or more gate electrodes;
• providing a second transistor chip having one or more source electrodes on a first side of the second transistor chip, one or more drain electrodes on a second side of the second transistor chip;
• treating the source electrodes on a first side of the second transistor chip with solder bumping;
• grinding the second side of the first transistor chip and the second side of the second transistor chip;
• applying a conductive layer to at least one of the second side of the first transistor chip and the second side of the second transistor chip;
• positioning the second side of the first transistor chip adjacent to the second side of the second transistor chip such that drain electrodes of the first transistor chip and drain electrodes of the second transistor chip are coupled together by the conductive layer;
• coupling source electrodes of the second transistor chip to a lead frame using the solder bumping;
• and
• coupling source electrodes of the first transistor chip to the lead frame using bond wires.