Routing instruction results to a register block of a subdivided register file based on register block utilization rate

A processor for processing instructions, the processor comprising:

• at least one processing pipeline having a plurality of execution units configured to execute the instructions;
• a register file having a plurality of register file entries configured to hold data, the register file sub-divided into a plurality of register blocks, each register block having at least two register file entries configured, wherein each register block is configured to receive results from a specific execution unit;
• and
• an instruction dispatch unit configured to select which one of the plurality of register blocks is to receive the results from executing the instructions,
• wherein the processor is configured to:
• calculate a utilization rate for one or more of the plurality of register blocks;
• and
• assign a register block to receive the results from executing an instruction based upon the utilization rate for that register block.

A processor for processing instructions, the processor comprising:

• at least one processing pipeline having a plurality of execution units configured to execute the instructions;
• a register file having a plurality of register file entries configured to hold data, the register file sub-divided into a plurality of register blocks, each register block having at least two register file entries, wherein each register block is configured to receive results from a specific execution unit;
• and
• an instruction dispatch unit configured to select for each instruction the issue queue to hold that instruction for execution and the execution unit to execute that instruction, wherein the dispatch unit comprises a counter to determine for each register block one of a number of available or in use register file entries in the respective register blocks,
• wherein the dispatch unit is configured to:
• preliminarily associate a specific register block with an instruction;
• determine, using the counter for the specific register block preliminarily associated with the instruction whether the specific register block preliminarily associated with the instruction is over-utilized;
• assign, in response to the specific register block preliminarily associated with the instruction being over-utilized, a register block to the instruction that is different than the specific register block preliminarily associated with the instruction;
• and
• assign, in response to the specific register block preliminarily associated with the instruction not being over-utilized, the specific register block preliminarily associated with the instruction;
• and
• wherein the processor is configured to:
• transmit the instruction with its assigned register block to the issue queue and the mapper.