Gate Isolation Features and Methods of Fabricating the Same in Semiconductor Devices

A semiconductor structure, comprising:

• a first fin and a second fin protruding from a substrate, the first and the second fins each including a stack of semiconductor layers;
• an insulating layer filling space between the first and the second fins;
• a metal gate stack engaged with the first and the second fins, wherein a first portion of the metal gate stack is disposed over the first and the second fins and a second portion of the metal gate stack is interleaved with the stack of semiconductor layers of each of the first and the second fins;
• and
• a dielectric feature disposed on the insulating layer and extending vertically through the metal gate stack, wherein the dielectric feature includes a first dielectric layer and a second dielectric layer, and wherein dielectric constant of the second dielectric layer is greater than that of the first dielectric layer.

A method, comprising:

• forming semiconductor fins protruding from a substrate and oriented lengthwise in a first direction;
• forming a first dielectric layer over the substrate to fill space between adjacent semiconductor fins;
• recessing the first dielectric layer to form a first trench and a second trench;
• forming a first dielectric feature in the first trench and a second dielectric feature in the second trench, wherein the first and the second dielectric features are oriented lengthwise along the first direction and each include a second dielectric layer and a third dielectric layer, and wherein dielectric constant of the second dielectric layer is less than that of the third dielectric layer;
• forming a placeholder gate over the semiconductor fins, wherein portions of the first and the second dielectric features are embedded in the placeholder gate;
• selectively removing the portion of the first dielectric feature embedded in the placeholder gate without removing any portion of the second dielectric feature;
• removing the placeholder gate to expose the portion of the second dielectric feature in a third trench;
• forming a metal gate stack in the third trench;
• recessing the metal gate stack to expose the second dielectric feature, wherein a top surface of the second dielectric feature is above a top surface of the recessed metal gate stack;
• and
• forming a fourth dielectric layer over the recessed metal gate stack, such that a top portion of the second dielectric feature is embedded in the fourth dielectric layer.