Method and system for distributing instructions in reconfigurable processor and storage medium

A system for distributing instructions in a reconfigurable processor, wherein the reconfigurable processor comprises an instruction fetch module, an instruction sync control module and an instruction queue module;

• the instruction fetch module is configured to distribute a plurality of to-be-run instructions to the instruction sync control module and the instruction queue module;
• the instruction sync control module is configured to control execution of instructions in the instruction queue module;
• the instruction queue module comprises a plurality of instruction queues;
• each instruction queue is provided with a plurality of instruction units sequentially arranged;
• each instruction queue corresponds to one instruction type;
• the system comprises:
• a Memory Sync ID Table configuring unit, configured to configure a format of a Memory Sync ID Table of each instruction type;
• the Memory Sync ID Table comprising a plurality of storage units sequentially configured;
• a first memory identification field storage bit and/or a second memory identification field storage bit being configured in each storage unit;
• each instruction type corresponding to a set number of first memory identification fields and/or second memory identification fields;
• an instruction fetch unit, configured to sequentially extract a first memory identification field and a second memory identification field of each instruction in the plurality of to-be-run instructions;
• a one-hot encoding unit, configured to:
• obtain one-hot encoding of the first memory identification field and/or one-hot encoding of the second memory identification field of each instruction;
• store the one-hot encoding of the first memory identification field and the one-hot encoding of the second memory identification field of each instruction in the corresponding Memory Sync ID Table based on an execution order of the plurality of to-be-run instructions;
• and
• send an instruction parameter of each instruction to each instruction unit of the corresponding instruction queue in the instruction queue module;
• a sync table generating unit, configured to obtain, by the instruction sync control module, dependency identification information of any one instruction type and other two instruction types based on one-hot encoding of first memory identification fields and one-hot encoding of second memory identification fields of each instruction type in the Memory Sync ID Table;
• and generate a sync table along a first data dimension based on the dependency identification information;
• the sync table comprising a first data dimension and a second data dimension converged with each other;
• the first data dimension of each instruction type corresponding to a storage bit number of the Memory Sync ID Table of each instruction type;
• and
• an instruction execution unit, configured to execute a corresponding instruction based on dependency of each type of instructions along the second data dimension of the sync table;
• a number of the second data dimension of each instruction type corresponding to a number of instruction units in the instruction queue;
• and call, by the instruction sync control module, the instruction parameter corresponding to each instruction in the instruction unit through the sync table while executing the corresponding instruction to execute each instruction in the plurality of to-be-run instructions.