Low power area efficient divided clock shifter scheme for high latency designs

A clock shifter circuit, comprising:

• shift register circuitry comprising a number of shift registers, wherein the shift registers are configured to operate according to a divided memory clock signal having a fraction of a memory clock frequency of a memory clock signal to delay data bits of memory access commands;
• first-in first-out (FIFO) circuitry configured to receive phase information of the data bits, and provide the received phase information to phase correction circuitry;
• and
• the phase correction circuitry configured to:
• receive the data bits from the shift register circuitry using the fraction of the memory clock frequency;
• receive the phase information from the FIFO circuitry;
• and
• output the data bits using the memory clock frequency after delaying the data bits based on the phase information.

A memory device, comprising:

• a three-dimensional memory array comprising threshold-type memory cells configured to be accessed using a memory clock signal having a memory clock frequency based on a memory access time;
• shift register circuitry configured to delay memory access commands using a divided memory clock signal having a fraction of the memory clock frequency;
• first-in first-out (FIFO) circuitry configured to receive and provide phase information of the memory access commands in coordination with the shift register circuitry;
• and
• phase correction circuitry configured to:
• receive the memory access commands and the phase information using the divided clock signal;
• use the memory clock signal to further delay the memory access commands based on the phase information using the memory clock signal having the memory clock frequency;
• and
• output the memory access commands using the memory clock signal having the memory clock frequency to access the threshold-type memory cells.