Implementation method and system of risc_v vector instruction set vsetvli instruction

A method for realizing vsetvli instructions in a risc_v vector instruction set, the method comprising the following steps:

• step S1:
• when a CPU is executed out of order, allocating vectag [n:0] information in a rename module to determine whether an instruction is a vsetvli instruction;
• Step S2:
• if the instruction is vsetvli instruction, performing vectag+1, if the instruction is not vsetvli instructions, keeping vectag unchanged;
• Step S3:
• distributing one or more vsetvli instructions to a csr module, and distributing one or more other vector instructions to a vpu module;
• Step S4:
• when the vectag information of one or more instructions is determined to be consistent with a vectag broadcast by an ROB module, transmitting the one or more instructions from a reserve station to an execution unit;
• and
• Step S5:
• completing execution of the one or more instructions, in the ROB module, graduating in order, and updating a register vectag when graduating.

A system for realizing risc_v vector instruction set vsetvli instructions, the system comprising a rename module, a dispatch module, a vpu module and an ROB module;

• wherein the system is used for implementing risc_v vector instruction set vsetvli instructions by performing methods comprising steps of:
• step S1:
• when a CPU is executed out of order, allocating vectag [n:0] information in a rename module to determine whether an instruction is a vsetvli instruction;
• Step S2:
• if the instruction is vsetvli instruction, performing vectag+1, if the instruction is not vsetvli instructions, keeping vectag unchanged;
• Step S3:
• distributing one or more vsetvli instructions to a csr module, and distributing one or more other vector instructions to a vpu module;
• Step S4:
• when the vectag information of one or more instructions is determined to be consistent with a vectag broadcast by an ROB module, transmitting the one or more instructions from a reserve station to an execution unit;
• and
• Step S5:
• completing execution of the one or more instructions, in the ROB module, graduating in order, and updating a register vectag when graduating.