Integrated circuit device and method

A method, comprising:

• generating a layout diagram of an integrated circuit (IC) device;
• and
• manufacturing the IC device based on the generated layout diagram,
• wherein
• said generating the layout diagram comprises:
• placing a first cell adjacent a second cell in the layout diagram, wherein the first cell comprises a first input/output (TO) pattern, the second cell comprises a second IO pattern corresponding to the first IO pattern, and the first IO pattern and the second IO pattern are in a first metal layer and aligned along a first axis;
• and
• routing, in the first metal layer, a connecting pattern between the first IO pattern and the second IO pattern, wherein the connecting pattern is contiguous to, and aligned along the first axis with, both of the first IO pattern and the second IO pattern, and
• the first metal layer is a metal-zero (M0) layer or a back-side-metal-zero (M0_B) layer.

A method of manufacturing an integrated circuit (IC) device in accordance with a layout diagram, the method comprising:

• forming a plurality of transistors over a substrate;
• and
• depositing a metal layer over the substrate, and patterning the metal layer to obtain a plurality of conductive patterns, wherein
• the plurality of conductive patterns comprises
• a first set of conductive patterns over and electrically coupled to a corresponding first set of transistors among the plurality of transistors, the first set of transistors electrically coupled into a first circuit corresponding to a first cell in the layout diagram, and
• a second set of conductive patterns over and electrically coupled to a corresponding second set of transistors among the plurality of transistors, the second set of transistors electrically coupled into a second circuit corresponding to a second cell in the layout diagram,
• the first and second sets of conductive patterns comprise a common conductive pattern, and
• the metal layer is a metal-zero (M0) layer or a back-side-metal-zero (M0_B) layer.