US 2023/0068097 A1Published application

Base layout cell

AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.

InventorsShang-Hsuan CIOU, Chih-Liang Chen, Hui-Zhong Zhuang, Chi-Yu Lu, Kuang-Ching Chang

Life of this patent

Estimating the term…

Loading patent…

Abstract

Systems, methods and devices are provided, which can include an engineering change order (ECO) base. A base layout cell includes metal layer regions, conductive gate patterns arranged above metal layer regions; oxide definition (OD) patterns, metal-zero layer over oxide-definition (metal-zero) patterns, at least one cut metal layer (CMD) pattern; and at least one via region. The base layout cell can be implemented in at least two non-identical functional cells. A first functional cell of the at least two non-identical functional cells includes first interconnection conductive patterns arranged connecting metal-zero structures corresponding to at least two metal-zero patterns in a first layout, and a second functional cell of the at least two non-identical functional cells includes second interconnection conductive patterns arranged connecting metal-zero structures corresponding to at least two metal-zero patterns in a second layout.

Claims20

Dependent claims

A method, comprising:

placing a base layout cell in a layout, wherein the base layout cell comprises:
first and second metal layer patterns extending in a first direction;
a plurality of active area layer patterns between the first metal layer pattern and the second metal layer pattern, wherein the plurality of active layer patterns extend in the first direction;
a plurality of conductive gate layer patterns extending in a second direction perpendicular to the first direction and traversing over the first and second metal layer patterns and over the plurality of active area layer patterns;
a plurality of contact layer patterns extending in the second direction between two conductive gate layer patterns of the plurality of conductive gate layer patterns, wherein at least one contact layer pattern of the plurality of contact layer patterns traverses over at least one active area layer pattern of the plurality of active layer patterns;
and
a cut metal layer extending in the first direction between two active area layer patterns of the plurality of active area layer patterns, wherein the cut metal layer is between at least two conductive gate layer patterns;
connecting one or more of the first and second metal layer patterns, the plurality of active area layer patterns, the plurality of conductive gate layer patterns, the plurality of contact layer patterns to represent a first circuit;
and
defining the first circuit based on a base mark of the base layout cell.

7 more elements

A base layout cell, comprising:

first and second metal layer patterns extending in a first direction;
a plurality of active area layer patterns between the first metal layer pattern and the second metal layer pattern, wherein the plurality of active layer patterns extend in the first direction;
a plurality of conductive gate layer patterns extending in a second direction perpendicular to the first direction and traversing over the first and second metal layer patterns and over the plurality of active area layer patterns;
a plurality of contact layer patterns extending in the second direction between two conductive gate layer patterns of the plurality of conductive gate layer patterns, wherein at least one contact layer pattern of the plurality of contact layer patterns traverses over at least one active area layer pattern of the plurality of active layer patterns;
and
a cut metal layer extending in the first direction between two active area layer patterns of the plurality of active area layer patterns,
wherein the cut metal layer is between at least two conductive gate layer patterns, and
wherein the base layout cell comprises one or more layout patterns common to a plurality of non-identical functional cell layouts.

5 more elements

A non-transitory computer-readable medium having instructions stored therein, which when executed by a processor of a hand held device, causes the processor to perform operations, the operations comprising:

placing, by the processor, a base layout cell in a layout, wherein the base layout cell comprises:
first and second metal layer patterns extending in a first direction;
a plurality of active area layer patterns between the first metal layer pattern and the second metal layer pattern, wherein the plurality of active layer patterns extend in the first direction;
a plurality of conductive gate layer patterns extending in a second direction perpendicular to the first direction and traversing over the first and second metal layer patterns and over the plurality of active area layer patterns;
a plurality of contact layer patterns extending in the second direction between two conductive gate layer patterns of the plurality of conductive gate layer patterns, wherein at least one contact layer pattern of the plurality of contact layer patterns traverses over at least one active area layer pattern of the plurality of active layer patterns;
and
a cut metal layer extending in the first direction between two active area layer patterns of the plurality of active area layer patterns, wherein the cut metal layer is between at least two conductive gate layer patterns;
connecting, by the processor, one or more of the first and second metal layer patterns, the plurality of active area layer patterns, the plurality of conductive gate layer patterns, the plurality of contact layer patterns to represent a first circuit;
and
connecting, by the processor, the first circuit to a second circuit.

7 more elements

Dependencies are inferred from the claim text.