Three-state memory device
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorMauricio Manfrini
Life of this patent
Estimating the term…
Abstract
The present disclosure relates to an integrated chip including a bottom electrode arranged within a dielectric layer. A memory element is directly over the bottom electrode and is arranged within the dielectric layer. A top electrode is directly over the memory element and is arranged within the dielectric layer. A conductive via is directly over the top electrode. A pair of lines that extend along opposing sidewalls of the top electrode are directly over, and intersect, an uppermost surface of the memory element. The pair of lines are directly under, and intersect, a lowermost surface of the via.
Claims20
An integrated chip, comprising:
- a bottom electrode arranged within a dielectric layer;
- a memory element directly over the bottom electrode and arranged within the dielectric layer;
- a top electrode directly over the memory element and arranged within the dielectric layer;
- and
- a conductive via directly over the top electrode,
- wherein a pair of lines that extend along opposing sidewalls of the top electrode are directly over, and intersect, an uppermost surface of the memory element, and wherein the pair of lines are directly under, and intersect, a lowermost surface of the via.
An integrated chip, comprising:
- a bottom electrode arranged within a dielectric layer;
- a memory element directly over the bottom electrode and arranged within the dielectric layer;
- a top electrode directly over the memory element and arranged within the dielectric layer, wherein a first perimeter of a lowermost surface of the top electrode is arranged within a second perimeter of an uppermost surface of the memory element;
- a conductive via directly over the top electrode;
- a first conductive line directly over the conductive via and extending along a first direction, wherein the first conductive line is disposed at a first height;
- and
- a second conductive line adjacent to the first conductive line, wherein the second conductive line extends along a second direction transverse to the first direction, and wherein the second conductive line is arranged on a sidewall of the first conductive line.
A method for forming an integrated chip, the method comprising:
- forming a memory element over a bottom electrode;
- depositing a first dielectric layer over the memory element;
- patterning the first dielectric layer to form a first opening in the first dielectric layer and directly over the memory element, wherein a distance between sidewalls of the first dielectric layer that define the first opening is less than a width of the memory element;
- depositing a first conductive material in the first opening to form a top electrode in the first opening and directly over the memory element;
- depositing a second dielectric layer over the top electrode and over the first dielectric layer;
- patterning the second dielectric layer to form a second opening in the second dielectric layer and directly over the top electrode;
- depositing a second conductive material in the second opening to form a first conductive line extending in a first direction and directly over the top electrode;
- patterning the second dielectric layer to form a third opening in the second dielectric layer and adjacent to the first conductive line;
- and
- depositing a third conductive material in the third opening to form a source line on a sidewall of the first conductive line and extending in a second direction transverse to the first direction, wherein the source line is electrically coupled to the top electrode.
Dependencies are inferred from the claim text.