Tapered Dielectric Layer for Preventing Electrical Shorting Between Gate and Back Side Via

A semiconductor device, comprising:

• a plurality of semiconductor channels stacked over one another vertically;
• a gate structure formed over the semiconductor channels, wherein each of the semiconductor channels is circumferentially surrounded by the gate structure, and wherein the gate structure extends in a first lateral direction;
• a first interconnect structure formed over the gate structure;
• a dielectric layer located below a bottommost one of the semiconductor channels, wherein a side surface of the dielectric layer is tapered in the first lateral direction;
• a conductive via located below the dielectric layer, wherein the dielectric layer prevents the conductive via from coming into direct physical contact with the gate structure;
• and
• a second interconnect structure located below the conductive via.

A method, comprising:

• forming a plurality of first semiconductor layers and second semiconductor layers over a front side of a substrate, wherein the first semiconductor layers interleave with the second semiconductor layers in a vertical direction;
• etching the first semiconductor layers and second semiconductor layers into a plurality of stacks, wherein the etching is performed such that a bottommost first semiconductor layer is etched to have a tapered profile in a cross-sectional view;
• replacing the bottommost first semiconductor layer with a dielectric layer, wherein the dielectric layer inherits the tapered profile of the bottommost first semiconductor layer;
• forming gate structures over the stacks, wherein the gate structures each extend in a first horizontal direction;
• forming a first interconnect structure over the gate structures;
• and
• forming a second interconnect structure over a back side of the substrate.